1. Field of the Invention
This invention relates to the logic circuit using field effect transistors (FET) and bipolar transistors, and more particularly, to the source-coupled FET-logic-type logic circuit to be used for digital integrated circuits.
2. Description of the Related Art
A prescribed signal (e.g. signal with 1/2 frequency of clock signal) has been obtained so far by inputting the reference signal to a T-flip-flop circuit and fetching the output signal of the T-flip-flop circuit.
For mobile radio equipment for communication, however, it may be necessary to separately fetch the signal with the same frequency as the reference signal and that with 1/2 frequency of the reference signal according to necessity.
Therefore, to configure the equipment with the source-coupled FET-logic (hereafter called SCFL)-type logic circuit, for example, the following logic circuit has been used.
That is, as is shown in FIG. 8, the reference signal input from the input terminal IN is input to a selection circuit directly or through the T-flip-flop circuit and the reference signal is output to the output terminal of the selection circuit. By switching the level of the switching terminal, either the signal with the same frequency as the reference signal or that with 1/2 frequency of it is output.
FIG. 1 shows the configuration of the T-flip-flop circuit and FIG. 2 the block diagram of the selection circuit.
As is illustrated in FIG. 1, one of the electrodes of level shift element LS1 is connected to a high-potential power supply V.sub.DD, while the other end is connected to one end of load elements LD1 and LD2.
Load elements LD1 and LD2 are connected, at the other end, to the drain electrodes of field effect transistors (FET) Q1 and Q2, respectively.
The drain electrodes of FETs Q1 and Q2 connect with the drain electrodes of FETs Q3 and Q4, respectively.
The source electrodes of the FETs Q1 and Q2 are connected each other, which are connected to the drain of FET Q5 whose gate electrode connects with the input terminal IN. Similarly, the source electrodes of the FETs Q3 and Q4 are connected to each other, the source gate electrodes further are connected to the drain electrode of FET Q6 whose gate electrode is connected to the input terminal IN. In addition, the source electrodes of FETs Q5 and Q6 are connected each other, and also to a low-potential power supply V.sub.SS by constant current source CC1.
The drain electrodes of the FETs Q1 and Q2 are connected to the gate electrodes of FETs Q7 and Q8 whose drain electrodes are connected to the high-voltage power source, and whose source electrodes are connected to one end of level shift elements LS2 and LS3, respectively. The other ends of level shift elements LS2 and LS3 are connect to the low-voltage power supply V.sub.SS by constant current source CC2 and CC3.
Meanwhile, one of the electrodes of level shift element LS4 is connected to the high-potential power supply V.sub.DD, and the other end thereof is connected to one end of load elements LD3 and LD4. The other ends of load elements LD3 and LD4 are connected to the drain electrodes of FETs Q9 and Q10. The drain electrodes of FETs Q9 and Q10 connect with the drain electrodes of FETs Q11 and Q12.
The source electrodes of the FETs Q9 and Q1O are connected each other, which are connected to FET Q13 whose gate electrode connects with the input terminal IN. Similarly, the source electrodes of the FETs Q11 and Q12 are connected each other, which are connected to FET Q14 whose gate electrode connects with the input terminal IN. In addition, the source electrodes of FETs Q13 and Q14 are connected each other, and also to the low-voltage power supply V.sub.SS by constant current source CC4.
The gate electrodes of FETs Q9, Q10, Q11, and Q12 connect with the gate electrodes of FETs Q4, Q3, Q1, and Q2, respectively. The drain electrodes of the FETs Q9 and Q10 connect with the gate electrodes of FETs Q15 and Q16 whose drains are connected to power supply Vdd and whose source electrodes connect with level shift elements LS5 and LS6, respectively.
Level shift elements LS5 and LS6 connect with the negative-voltage power supply V.sub.SS through level shift element LS7 and constant current source CC5 and through level shift element LS8 and constant current source CC6, respectively.
In addition, the junction between level shift elements LS6 and LS8 connects with the gate electrodes of FETs Q1 and Q11. Similarly, the junction between level shift elements LS5 and LS7 connects with the gate electrodes of FETs Q2 and Q12. The output terminal Q connects with the junction between level shift element LS7 and constant current source CC5 and output terminal Q with level shift element LS8 and constant current source CC6 respectively.
The following describes the configuration of the selection circuit in FIG. 2. This selection circuit comprises level shift elements LS1 through LS3, load elements LD1 and LD2, FETs Q1 through Q8, and constant current sources CC1 through CC3, which has the same configuration as the portion shown by the reference numeral 10 of the T-flip-flop circuit in FIG. 1.
Therefore, only the portion different from the circuit in FIG. 1 is described below. In FIG. 2, input terminals A, A, B and B are connected to the gate electrodes of FETs Q1 through Q4, respectively. The gate electrodes of FETs Q5 and Q6 connect with switching terminals SW and SW, respectively. Output terminals Q and Q are connected to the junction between level shift element LS3 and constant current source CC3 and that between level shift element LS2 and constant current source CC2 respectively.
In the SCFL-type logic circuit thus configured, if switching terminal SW is brought under high level, the signal with the same frequency as the input signal is output. Meanwhile, if switching terminal SW is brought under low level, the signal with 1/2 frequency of the input signal is output.
However, the SCFL-type logic circuit having the configuration has the following problem. That is, because the circuit requires a selection circuit in addition to T-flip-flop circuit, the number of elements increases. Therefore, a large area is necessary, resulting in decrease of integration.
In view of the input terminal side, because the fan-in count equals 2, the current driving capacity at the first stage of this circuit must be increased. Therefore, it is necessary to increase the current to be given to the first-state circuit. This interrupts the power consumption from decreasing. On the contrary, unless the current to be given to the first stage is increased, a high circuit operation cannot be obtained.